Phase jitter tracker
US4953186A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 1988 |
| Grant date | Aug 28, 1990 |
| Priority date | — |
| Expiry date | Feb 19, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/123
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The jitter tracker of the present invention uses a decision-directed error signal as an input to a feedback loop. The error signal is filtered and coupled to a phase locked loop centered at the center of the jitter tracking frequency range, which in the preferred embodiment is 55 Hz. The frequency width and center track and lock frequencies are set by a loop filter. A second order loop is used to acquire the frequency and phase jitter within an acceptable range. Once within this range, a first order loop is used to lock the amplitude to the input signal. The amplitude and phase values are subtracted from the incoming signal so that a new error may be calculated. In the preferred embodiment, the jitter tracker of the present invention is implemented in a digital signal processor. The jitter tracker of the preferred embodiment of the present invention comprises two filter loops. The first loop is used to generate the magnitude of the jitter error. The second loop generates the phase of the jitter error. The input to the jitter tracker is the quadrature portion of a normalized error term. This quadrature portion is multiplied by the cosine of the output of the error loops to generate …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.