Method for inter-processor data transfer
US4956771A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 24, 1988 |
| Grant date | Sep 11, 1990 |
| Priority date | — |
| Expiry date | May 24, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9047
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method for transfer of data between multiple tasks in a host computer and multiple tasks in an intelligent controller. One or more memory buffers for holding the data to be transferred are allocated to each task. Each connection between corresponding tasks in the host and the controller is provided with a set of queues for controlling access by the controller to the memory buffers. An output queue contains descriptions of output buffers holding data for transfer from the host to the controller. A buffer queue contains descriptions of input buffers available for transfer of data from the controller to the host, a return queue contains descriptions of output buffers available for transfer of data from the host to the controller, and an input queue contains descriptions of input buffers holding data that has been transferred from the controller to the host. The queues contain pointers to extended control blocks, each containing a virtual data pointer and a physical data pointer to a specified buffer. When data is to be transferred, a description of a selected buffer is provided to the controller. When the controller has resources available, the host is notified and a description of …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.