Matrix arithmetic circuit for processing matrix transformation operations
US4956801A · kind A · utility
45Cited by
3References
6Claims
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Key dates
| Filing date | Sep 15, 1989 |
| Grant date | Sep 11, 1990 |
| Priority date | — |
| Expiry date | Sep 15, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A matrix arithmetic circuit for processing matrix transformation operations includes a random access memory (RAM) for storing a plurality of numbers in Modulo 256 with multiple tap points numbers format. A multiplier multiplies two of the Modulo 256 numbers in RAM to obtain a product. The product is normalized and added to a third Modulo 256 number stored in the RAM to obtain a result. The result is stored in the RAM and coupled to the data processing system for use in matrix transformation operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.