Arbiter circuit for establishing priority control of read, write and refresh operations with respect to memory array
US4956820A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 26, 1988 |
| Grant date | Sep 11, 1990 |
| Priority date | — |
| Expiry date | Feb 26, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arbiter circuit providing priority control of dynamic memory operations as a memory access signal control circuit which regulates the order in which dynamic memory access signals, such as read, write and refresh signals, are executed in effecting particular operating functions of a dynamic memory. The arbiter circuit has a first circuit element to temporarily hold a given access signal or signals, a second circuit element to inhibit transfer of any access signal when another access signal is already being executed, a third circuit element to synchronize individual access signals that are generated asynchronously, and a fourth circuit element to reset arbiter circuit upon the end of each access signal. The memory access signals or request signals are queued as necessary according to a priority allocation such that a write request signal heads the priority list, followed by a refresh request signal and a read request signal in order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.