CMOS parallel-serial multiplication circuit and multiplying and adding stages thereof
US4958313A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 6, 1989 |
| Grant date | Sep 18, 1990 |
| Priority date | — |
| Expiry date | Feb 6, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3872
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated CMOS multiplication circuit is operated in a parallel-serial mode and executes binary multiplication of a multiplicand and multiplier within the period of a system clock signal by an improved implementation of the two's complement method. The multiplication circuit includes an input shift register for receiving the multiplicand bits in parallel and reading them out serially as clocked by an internal clock signal of higher frequency than the system clock signal, a single chain of multiplying stages each receiving a respective one of the multiplier bits and the serially read-out multiplicand bits and performing successive partial product operations thereon, a parallel adder having a corresponding number of adding stages for successively adding the sum and carry bit outputs of the multiplying stages, an output shift register for serially receiving the output bits of the parallel adder, and a clock driver which generates the higher frequency internal clock signal from the system clock signal. Specific configurations are provided for CMOS circuits implementing the improved parallel-serial multiplier. The clock driver preferably uses a ring oscillator to derive the higher f…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.