Apparatus, method and data structure for validation of kernel data bus
US4958347A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 1988 |
| Grant date | Sep 18, 1990 |
| Priority date | — |
| Expiry date | Nov 23, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus, method and data structure for validating the data bus of a microprocessor-based unit under test in which bit patterns having half as many bits as the width of the data bus are applied to the data bus along with another bit pattern which is either the complemented or true replication of the bit pattern. Evaluation of the resulting bit patterns on the data bus permits a validation of the entire width of the data bus which, if no faults are reported, obviates not only probing of the data bus by the operator but data bus diagnosis, as well. A particular data structure of a preferred bit pattern sequence avoids any fault on any data line being reported as a pass.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.