Semiconductor memory device with error check and correcting function
US4958352A · kind A · utility
40Cited by
5References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 4, 1988 |
| Grant date | Sep 18, 1990 |
| Priority date | — |
| Expiry date | Oct 4, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An EEPROM having an ECC circuit further comprises a counter circuit. The ECC circuit checks and corrects bit errors included in data read out from a memory cell array. In addition, the ECC circuit generates a predetermined signal every time it corrects a bit error. The counter circuit counts a predetermined signal generated from the ECC circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.