Output buffer with ground bounce control
US4959565A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 1989 |
| Grant date | Sep 25, 1990 |
| Priority date | — |
| Expiry date | Feb 10, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/998
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A novel output buffer is described which includes a plurality of pull up transistors connected in parallel and/or a plurality of pull down transistors connected in parallel. A desired amount of resistance is included in the path connecting the gates of the pull up transistors, and in the path connecting the gates of the pull down transistors, thereby providing a distributed RC network causing pull up and pull down transistors to turn on in sequence. This is designed to keep the rate of change of the pull up and pull down current constant, thus reducing ground and Vcc bounce. In another embodiment, a single pull up transistor and/or a single pull down transistor is used. The single transistors have a relatively high gate resistance such that along the channel width of the transistor, the gate capacitance and the gate resistance operates as a distributed RC network. In this manner, portions of the channel begin conducting sequentially, as is the case where a plurality of pull up and pull down transistors are used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.