Write-shared cache circuit for multiprocessor system
US4959777A · kind A · utility
62Cited by
5References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 27, 1987 |
| Grant date | Sep 25, 1990 |
| Priority date | — |
| Expiry date | Jul 27, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A "write-shared" cache circuit for multiprocessor systems maintains data consistency throughout the system and eliminates non-essential bus accesses by utilizing additional bus lines between caches of the system and by utilizing additional logic in order to enhance the intercache communication. Data is only written through to the system bus when the data is labeled "shared". A write-miss is read only once on the system bus in an "invalidate" cycle, and then it is written only to the requesting cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.