Clock recovery apparatus including a clock frequency adjuster
US4959846A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 1989 |
| Grant date | Sep 25, 1990 |
| Priority date | — |
| Expiry date | Sep 11, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/044
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital phase acquisition circuit includes circuits for detecting an edge of incoming data and a plurality of candidate clock phases, the circuitry further including logic for determining when the data undergoes a predetermined phase transition and at least one candidate phase which undergoes a digitally equivalent transition close in time to the data transition so as to enable the candidate phase to be used for choosing an appropriate clock phase for recovering information representative of the data. The circuit further includes logic for comparing a frequency of the chosen clock pulse and the data and adjusting at least one of these frequencies when a predetermined amount of drift therebetween is detected. The invention allows clock to be recovered within 1 bit time of a predetermined data transition occurring and allows an appropriate clock to be maintained through an entire packet regardless of packet length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.