Process for making a self aligned vertical field effect transistor having an improved source contact
US4960723A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 30, 1989 |
| Grant date | Oct 2, 1990 |
| Priority date | — |
| Expiry date | Mar 30, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved method for making a self-aligned vertical field effect transistor is provided wherein a nitride sidewall spacer is formed around a polysilicon gate, and an oxide sidewall spacer, which may be heavily doped with an n-type dopant, is formed covering the silicon nitride sidewall spacer. The silicon nitride sidewall spacer allows the oxide sidewall spacer of a conventional self-aligned vertical field effect transistor process to be removed partially or completely before making ohmic contact to the source thus increasing the contact area between the source and the source electrode and eliminating reliability problems related to n-type doped oxide in contact with aluminum electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.