BiCMOS process
US4960726A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1989 |
| Grant date | Oct 2, 1990 |
| Priority date | — |
| Expiry date | Oct 19, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0109
Abstract
A method for manufacturing a BiCMOS device includes providing a semiconductor substrate including first and second electrically isolated device regions. A layer of insulating material is formed over the first device region, and a layer of conductive material is formed conformally over the device. Portions of the conductive layer are removed to leave a base contact on the surface of the second device region and an insulated gate contact over the surface of the first device region. A FET is formed in the first device region having a channel under the insulated gate. A vertical bipolar transistor is formed in the second device region having a base region contacting the base contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.