Microprocessor system having cache directory and cache memory and hardware for initializing the directory
US4961136A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 4, 1989 |
| Grant date | Oct 2, 1990 |
| Priority date | — |
| Expiry date | Dec 4, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor includes an initializing section for generating a reset signal, in response to an input reset instruction. A controller outputs a bus acquisition request to the microprocessor, in response to the reset signal output from the initializing section. The microprocessor is reset in response to the reset signal output from the initializing section, and generates a bus acquisition acknowledge in accordance with the bus acquisition request output from the controller, thereby releasing a bus and holding an operation state. The controller initializes a cache directory, using the bus which is released in accordance with the bus acquisition acknowledge from the microprocessor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.