Method of and apparatus for generating variable time delay
US4961169A · kind A · utility
21Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1987 |
| Grant date | Oct 2, 1990 |
| Priority date | — |
| Expiry date | Dec 23, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/00
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A variable length shift register comprises a memory cell array (1) having memory cells arranged in a matrix of row and columns, a variable length ring pointer (2) responsive to a bit length selecting signal for sequentially activating a single row in the memory cell array in a recirculated manner within a predetermined constant range, an input buffer (4) for writing data into a memory cell of the activated row, and an output buffer (5) for reading out data from a memory cell of the activated row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.