Decoder for a memory address bus
US4961172A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 1988 |
| Grant date | Oct 2, 1990 |
| Priority date | — |
| Expiry date | Aug 11, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit constructed in accordance with my invention includes a microprocessor for generating addresses on an address bus, a plurality of memory devices, and a decoder for decoding the address on the address bus and generating select signals in response thereto. Of importance, the memory devices are also coupled to the address bus. A memory enable circuit is provided for enabling the memory devices before the decoder generates the select signals. Thus, the time required by the decoder to decode address signals does not add to the delay between the time an address is asserted by the microprocessor and the time one of the memory devices responds by providing data. In one embodiment, the memory enable circuit is incorporated into the bit line decoder of the memory devices. Thus, if one of the bit lines of the plurality of memory devices is selected to provide data, the memory device is enabled. Since the word line decoder is generally slower than the bit line decoder, inclusion of the memory enable circuit into the bit line decoder will not slow the memory devices. Also in one embodiment, the bit line decoder is programmable so that the memory devices can be mapped into different blo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.