Extended errors correcting device having single package error correcting and double package error detecting codes
US4961193A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 1988 |
| Grant date | Oct 2, 1990 |
| Priority date | — |
| Expiry date | Nov 28, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for correcting data words from a memory is provided in which coded data is divided into a plurality of multi-bit packages of b bits each. The coded data comprises n-bit words with r error correcting code bits and n-r data bits. The invention is capable of correcting one package which has suffered at least one hard failure and a single soft error located in a different package. The invention involves the use of an error correcting code which gives a first syndrome when the data word has suffered a first error coming from at least one error in a first package and a single error in a different second package, which also gives a second syndrome when the data word has suffered a second error coming from at least one error in the above first package, and a single error in a third package. The error correcting code is such that equality of the first and second syndromes results in the equality of the first and second errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.