Method of forming a defect-free semiconductor layer on insulator
US4962051A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 18, 1988 |
| Grant date | Oct 9, 1990 |
| Priority date | — |
| Expiry date | Nov 18, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/097
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved method of fabricating a defect-free semiconductor layer and a semiconductor on insulator structure is provided by forming an isoelectronically doped semiconductor layer between a substrate and an semiconductor layer. The isoelectronic dopant atoms are different in atomic size than the atoms of the semiconductor material, thus misfit dislocations are created at the interface of the isoelectronically doped semiconductor layer due to lattice mismatch. Impurities and defects are not only gettered to the misfit dislocation sites, but are also prevented from propagating to the epitaxial layer. These misfit dislocations are thermally stable and are confined in a plane parallel to the interfaces of the isoelectronically doped semiconductor layer, thus very effective gettering agents. If the isoelectroncially doped semiconductor layer us also a heavily doped buried layer, no misfit dislocations are desired because the buried layer is an active device layer. In this case the isoelectronic dopant atoms may offset the non-isoelectronic dopant atoms in atomic size, thus no misfit dislocations are formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.