Input protection circuit for MOS device
US4962320A · kind A · utility
6Cited by
7References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 13, 1989 |
| Grant date | Oct 9, 1990 |
| Priority date | — |
| Expiry date | Jul 13, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input protection circuit for MOS devices includes a first resistor and a first parasitic bipolar transistor connected between an input pad and an input buffer circuit of a MOS device. The input protection circuit for MOS devices further includes a second resistor and a second parasitic bipolar transistor connected at a preceding stage of the input buffer circuit so that the gate oxide film of the input buffer circuit can be protected from being damaged by static charges or a voltage which is accidentally generated, without increasing the pattern size of the first parasitic bipolar transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.