Sample-hold amplifier circuit
US4962325A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 1989 |
| Grant date | Oct 9, 1990 |
| Priority date | — |
| Expiry date | Sep 26, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/303
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An auto-zeroing sample-hold amplifier capable of tracking an input voltage and, when designated, sampling and accurately holding an input voltage with no gain or offset errors includes input and output buffers with complementary, equal-magnitude offsets for minimizing offset voltage errors. An input voltage is sampled across a primary hold capacitor as well as a secondary hold capacitor [at the amplifier output to] in a sample mode. In a hold mode, the capacitors, in conjunction with the buffers and a transconductance amplifier, form a negative feedback loop around the transconductance amplifier to hold the sampled voltage and reduced voltage excursions at the output of the sample-hold amplifier. A special cancellation switch and capacitor are included for differentially cancelling voltage errors caused by switch charge feed-through onto the primary hold capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.