Arbiter circuit for processing concurrent requests for access to shared resources
US4962379A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 1988 |
| Grant date | Oct 9, 1990 |
| Priority date | — |
| Expiry date | Nov 18, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arbiter circuit is disclosed for processing requests made at least two subsystems in a multiprocessor system for access to a resource shared by the subsystems. The arbiter circuit includes an SR flip-flop composed of a pair of NAND gates. The flip-flop is operative in response to a time-staggered request signals from the subsystems to provide a request acknowledging signal to the shared resource. When two request signals are simultaneously supplied to the arbiter circuit, the outputs from the pair of NAND gates tend to stay at an intermediate level between the normal two distincitive logic levels, failing to produce an acknowledgment signal. However, the intermediate level of the NAND gate outputs is sensed by a NOR gate to a trigger a switching device into conduction, by means of which one of the intermediate NAND gate outputs is positively shifted to either of the active logic levels for the generation of an acknowledgement signal to the shared resources. Thus, one of the two subsystems is allowed access to the shared resource.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.