Digital to analog converter with compensation memory addressed by lower order bits
US4963870A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 23, 1989 |
| Grant date | Oct 16, 1990 |
| Priority date | — |
| Expiry date | Oct 23, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital/analog converting device comprises a first digital/analog converter for converting upper M bits of an input digital signal into a first analog signal; a memory for receiving, as address data, at least a digital signal of lower N bits of the input digital signal to output lower-bit-output-approximate data of S (S>N) bits in response to the address data; a second digital/analog converter for converting digital data at least including the S-bit lower-bit-output-approximate data into a second analog signal; and an analog adder for outputting an added analog signal obtained by adding the first and second analog signals at a predetermined ratio. The S-bit lower-bit-output-approximate data are set such that, supposing a level change of the added analog signal with respect to a change of an LSB of the upper M bits being .DELTA.L, a minimum step increase of the digital signal of lower N bits causes a level of the added analog signal to increase by about .DELTA.L/2.sup.N.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.