Substrate structures for InP-based devices
US4963949A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1988 |
| Grant date | Oct 16, 1990 |
| Priority date | — |
| Expiry date | Sep 30, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/936
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate structure for an InP-based semiconductor device having an InP based film is disclosed. The substrate structure includes a substrate region having a lightweight bulk substrate and an upper GaAs layer. An interconnecting region is disposed between the substrate region and the InP-based device. The interconnecting region includes a compositionally graded intermediate layer substantially lattice-matched at one end to the GaAs layer and substantially lattice-matched at the opposite end to the InP-based film. The interconnecting region further includes a dislocation mechanism disposed between the GaAs layer and the InP-based film in cooperation with the graded intermediate layer, the buffer mechanism blocking and inhibiting propagation of threading dislocations between the substrate region, and the InP-based device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.