Direct digital synthesizer driven phase lock loop frequency synthesizer
US4965533A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 1989 |
| Grant date | Oct 23, 1990 |
| Priority date | — |
| Expiry date | Aug 31, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1806
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency synthesizer which uses a direct digital synthesizer (DDS) to drive a phase lock loop. The DDS generates a highly accurate periodic signal of a frequency selected from a plurality of reference frequencies. A phase lock loop receives the DDS generated reference signal and a divide-by-N signal for generating an output signal at a frequency determined by the divide-by-N signal. The frequency resolution of the phase lock loop is N times the reference signal. In a second embodiment, the DDS is incorporated within the feedback path of the phase lock loop. An input reference frequency signal is provided to the phase lock loop with the DDS clock signal provided as a function of the phase lock loop output frequency. The DDS receives an input frequency control signal which determines the DDS step size. The synthesizer output frequency is a function of the input reference , the number of bits in the digital word of the frequency control signal and the DDS step size as determined by the frequency control signal. Optional dividers may be provided in the feedback path which may further affect the synthesizer output frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.