Semiconductor package with ground plane
US4965654A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1989 |
| Grant date | Oct 23, 1990 |
| Priority date | — |
| Expiry date | Oct 30, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A plastic encapsulated semiconductor package in which the connecting lead frame members are deposited over the surface of the device together with a covering ground plane so as to provide enhanced electrical and thermal coupling of the members and the device and so reduce the signal to noise ratio by a factor or greater than three over that available in other similar plastic encapsulated packages while simultaneously improving the transfer of heat out of the package. In particular, a lead frame having a plurality of conductors is attached to a major active surface of a semiconductor chip via a ground plane which, in the preferred embodiment, is a multilayered structure containing an insulated integral, uniform ground plane positioned between the lead frame and the chip and adhesively and insulatively joined to both of them. Wires connect terminals on the major active surface of the semiconductor chip to the ground plane and to selective lead frame conductors. The lead frame, the ground plane structure, the semiconductor chip, and the wires which connect the semiconductor chip terminals to the ground plane and to selected lead frame conductors are encapsulated with a suitable insula…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.