Multiple processor system having shared memory with private-write capability
US4965717A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1988 |
| Grant date | Oct 23, 1990 |
| Priority date | — |
| Expiry date | Dec 13, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. Memory references. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references by the multiple CPUs are voted by each of the memory modules. A private-write area is included in the shared memory space in the memory modules to allow functions such as software voting of state information unique to CPUs. All CPUs write state information to their private-write area, then all CPUs read all the private-write areas for functions such as detecting differences in interrupt cause or the like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.