Compiler system using reordering of microoperations to eliminate interlocked instructions for pipelined processing of assembler source program
US4965724A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 29, 1988 |
| Grant date | Oct 23, 1990 |
| Priority date | — |
| Expiry date | Feb 29, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compiler system compiles a source program described with assembler instructions, each of which defines microoperations, into a target program for use in a digital signal processor. If two of the assembler instructions are interlocked with each other and if another assembler instructions which is not associated with the interlocked instructions is present, it is inserted between the interlocked instructions to thereby reorder the microoperations of the source program. Thereafter, the microoperations thus reordered are combined so as not to conflict with each other with regard to the fields of the assembler instructions and resources used by the assembler instructions. Prior to combining the microoperations, whether or not a basic block of assembler instructions included in the source program having a loop may be determined. If so, a head portion of the basic block forming the loop may then be transferred to a tail portion of the basic block forming the loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.