Graphics system with programmable tile size and multiplexed pixel data and partial pixel addresses based on tile size
US4965751A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 1987 |
| Grant date | Oct 23, 1990 |
| Priority date | — |
| Expiry date | Aug 18, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphics system uses a programmable tile size and shape supported by a frame buffer memory organization wherein (X, Y) pixel addresses map into regularly offset permutations on groups of RAM address and data line assignments. This allows one RAM in eac group to be accessed with a memory cycle in unison with one RAM in each other group, up to the number of groups. During such a memory cycle each RAM can receive a different address. A tile is the collection of pixel locations associated with a collection of addresses sent to the RAM's. Because of the regular nature of the permutations these locations may be regions bounded by a single boundary that may be rectangular and of varying size and shape. Changing the mapping of (X, Y) pixel addresses to RAM addresses for the groups changes the size and shape of the tiles. A pixel data/partial address muliplexing method based on programmable tile size reduces the number of interconnections between a pixel interpolator and the frame buffer without significantly increasing the number of bus cycles needed to transfer the information. Tiles are cached. Tiles for RGB pixel values are cached in an RGB cache, while Z values are cached in a separa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.