Mixed size radix recoded multiplier
US4965762A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 15, 1989 |
| Grant date | Oct 23, 1990 |
| Priority date | — |
| Expiry date | Sep 15, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5336
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array multiplier utilizing a predetermined recoding algorithm minimizes operating speed by using two different radices. Special product terms must be formed to implement the recording algorithm. In order to avoid delaying the computation of partial products until after the time special products are formed, two recoding radices may be used. Partial products can be calculated from terms formed by a smaller sized radix during the same time the special product terms are being calculated. Initial use of the smaller radix eliminates an immediate need for the special product bits which improves multiplier speed by minimizing time required to form a final product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.