Gallium arsenide depletion made MESFIT logic cell
US4965863A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 2, 1987 |
| Grant date | Oct 23, 1990 |
| Priority date | — |
| Expiry date | Oct 2, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/05
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gallium arsenide logic design system is described for designing custom or semi-custom LSI integrated circuits using standard cells from a cell library. D-MESFET transistors and Schottky diodes are used for implementing the cell types in gallium arsenide to produce performance levels of less than 150 pico-second per gate propagation delay. Each integrated circuit die is built from a cell library containing three standard cells. The limitation on the number of standard cells used for logic design allows for fast and efficient turnaround time between logic design and fabrication. A minumum number of masks are required for implementing the custom integrated circuit due to the efficient design of the cell types. The placement and interconnect of the cells on the die are also performed in an efficient manner due to the predefined allowable locations for cell placement and the predefined allowable route channels for the interconnect. A clock amplifier cell is described for the cell library which differentially phase corrects a two-phase clock signal to ensure that the two clock lines are perfectly out of phase at all times. The combination of this strictly controlled two-phase clock wit…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.