Substrate package
US4966284A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1989 |
| Grant date | Oct 30, 1990 |
| Priority date | — |
| Expiry date | Mar 31, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67386
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A sealable contamination proof container package bottom and top for storing and transporting a plurality of substrates or wafers in a robotic wafer carrier. The package bottom includes four sides, a continuous vertical surface for tape sealing surrounding the four sides, a lip positioned on a vertical edge, opposing hook latches on opposing sides, opposing hand grip recesses on the opposing sides and a raised bottom surface for package stacking. The package top includes four sides, a continuous vertical surface for tape sealing surrounding the four sides, a lip positioned on the vertical surface, opposing hook catches on the opposing side, a top surface with raised stacking surfaces, and two rows of wafer support springs positioned on bars on the underside of the top surface. The package top and bottom halves provide that the robotic wafer carrier mates between the package top and package bottom with the wafers or substrates in the carrier. The package top and bottom mate with the upper lip engaged with the lower lip, and the catches of the top engage with the latches of the bottom. The package halves are designed in such a fashion as to prevent wafer or substrate damage upon openi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.