Semiconductor chip production and testing processes
US4967146A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 1989 |
| Grant date | Oct 30, 1990 |
| Priority date | — |
| Expiry date | May 15, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12042
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Precisely controlled grooves are formed in a semiconductor wafer as part of a total photolithographic process of producing the circuitry and the V-grooves for precise registration of the circuitry relative the edges of the individual chips of the wafer. The same registration facilitates automated electrical testing of each of the chip circuits on the wafer prior to the controlled disassembly of the array of chips into individual die. The design of the electrical connections on the array before disassociation into individual die also facilitates a mass burn-in of the circuits which burn-in tends to identify and eliminate parts subject to early failure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.