Microcomputer building block
US4967326A · kind A · utility
30Cited by
15References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 9, 1986 |
| Grant date | Oct 30, 1990 |
| Priority date | — |
| Expiry date | Dec 9, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Single chip microcomputers with program stored in on-chip RAM combined by non-shared communication links each having an input channel and an output channel, each channel having a data register and process register used for synchronizing processes executed in different microcomputers in an array. Each process on a chip has a workspace. Constant bit size instructions have function and data portions. Scheduling/descheduling of processes in each microcomputer occur by forming a linked list in the workspaces for active processs. Each workspace identifies the next process to be executed and the next instructon for its own process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.