Bit density controller
US4967389A · kind A · utility
11Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 22, 1987 |
| Grant date | Oct 30, 1990 |
| Priority date | — |
| Expiry date | Oct 22, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4915
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A bit density controller is capable of transmitting no more than 15 consecutive 0-bits to be sent serially in a data bit sequence, without a 1-bit, for operating on the AT&T T1 network. The bit density controller includes a state machine having a state index and a substitution device coupled to the state machine. The bit density controller additionally can include a buffer for storing at least one frame of the data bit sequence, a memory for storing overhead bits, and an overhead bit inserter for inserting overhead bits into the data bit sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.