Semiconductor integrated circuit device
US4967396A · kind A · utility
27Cited by
4References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 29, 1990 |
| Grant date | Oct 30, 1990 |
| Priority date | — |
| Expiry date | Jan 29, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/911
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a dynamic type RAM and, more particularly, to a dynamic type RAM formed using one-element type dynamic memory cells each comprised of a data storing capacitor and an address selecting MOSFET. Divided word lines are arranged such that one divided word line intersects another at a point of discontinuity of the other divided word line adjacent to a joint of the one divided word line to the corresponding word line. This prevents generation of an array noise due to coupling capacitances, and thus improves the read margin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.