Dynamic RAM controller
US4967397A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 1989 |
| Grant date | Oct 30, 1990 |
| Priority date | — |
| Expiry date | May 15, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM controller wherein the outputs of a 74F538 integrated circuit provides RAS signals to the banks of a DRAM array, respectively, where the 74F538 is located at the array. A microprocessor utilizing the array provides appropriate memory address signals, a refresh request signal and a RAS timing signal. A PAL16L8B responsive to the memory address, refresh request signal and RAS timing signal encodes the memory address into a digital RAS signal having fewer bits than the number of memory banks. The digital RAS signal represents the selected bank for a memory access cycle. The digital RAS signal is conveyed in parallel on a bus coupling the to the 538. The generates an enable signal in response to the RAS timing signal to enable the 538 during memory access cycles. During memory access cycles, the 538 decodes the digital RAS signal to enable one of the outputs thereof in accordance therewith. The P input of the 538 receives a refresh pulse generated by the in response to the refresh request signal. When the refresh pulse is active and the 538 is disabled, all of the outputs thereof switch polarity so as to effect a refresh cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.