Method for manufacturing MOS/CMOS monolithic integrated circuits including silicide and polysilicon patterning
US4968645A · kind A · utility
33Cited by
13References
3Claims
0Family size
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Key dates
| Filing date | Dec 15, 1988 |
| Grant date | Nov 6, 1990 |
| Priority date | — |
| Expiry date | Dec 15, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/136
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A monolithic integrated circuit of either the MOS or CMOS type comprises an intermediate layer of polycrystalline silicon, a layer of a silicide of a refractory metal overlying said polycrystalline silicon layer, and regions of preset area and preset paths formed in the polycrystalline silicon layer and the silicide layer; the preset area regions and preset paths forming respectively high resistivity resistances and low resistivity interconnection lines for an intermediate connection level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.