Process for fabricating small size electrodes in an integrated circuit
US4968646A · kind A · utility
5Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 1989 |
| Grant date | Nov 6, 1990 |
| Priority date | — |
| Expiry date | Dec 12, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D44/041
Abstract
According to the invention, a first layer of conductive material (11) is submitted to an incomplete etching operation in the presence of a mask (13). After elimination of the mask, a second layer of conductive material is deposited, and the thus-obtained result is submitted to an etching operation without a mask, so allowing the inter-electrode gaps to be reduced. The process provides a very tight electrode configuration, and is particularly suited to charge-coupled devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.