Program routine vectoring circuit for selectively using either stored interupt instructions or incoming interupt handling instructions
US4969090A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 1987 |
| Grant date | Nov 6, 1990 |
| Priority date | — |
| Expiry date | Sep 11, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A program routine vectoring system for use in a data processing system has a central processing unit and input circuitry for receiving interrupt information. The system includes read only memory for storing address information and instructions to be executed by the central processing unit, a signalling circuit for signalling the central processing unit when the input circuitry receives an interrupt request, to cause the central processing unit to retrieve initial address information from the read only memory, a decoder for decoding the retrieved address information supplied by the central processing unit and for producing a first signal if certain address information is supplied, and a second signal if other address information is supplied, and a multiplexer responsive to the first signal for supplying to the read only memory first instruction address information to cause the read only memory to supply to the central processing unit a first address in the read only memory containing instructions for processing the interrupt request, and responsive to the second signal for supplying to the read only memory second instruction address information to cause the read only memory to suppl…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.