Resettable latch circuit
US4970406A · kind A · utility
54Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1989 |
| Grant date | Nov 13, 1990 |
| Priority date | — |
| Expiry date | Jun 26, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356043
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reset circuit incorporated into a latch circuit which comprising a follow portion and a hold portion and generates an output signal at an output terminal in response to an input data signal and a clock signal. A reset signal is applied, via a diode, to the output terminal which causes the output terminal to immediately assume the state of the reset signal without any intervening gate delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.