Packaged semiconductor device with test circuits for determining fabrication parameters
US4970454A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 1990 |
| Grant date | Nov 13, 1990 |
| Priority date | — |
| Expiry date | Mar 15, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test circuit (40) fabricated in an integrated circuit and connected to an I/O pin (36) of the packaged device (32) for providing information indicative of substrate process parameters. The test circuit (40) comprises a test transistor (24) connected to a pin (36) of the packaged device (32), and an isolation circuit (52) responsive to a signal on an input test terminal (48) for activating the test transistor (24). The isolation circuit (52) is responsive to the absence of the test signal for isolating the test transistor (24) from the pin (36), and thus isolating it from other functional circuitry (54) of the integrated circuit which is also connected to the pin (36).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.