Analog/digital phase locked loop
US4970474A · kind A · utility
22Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 14, 1989 |
| Grant date | Nov 13, 1990 |
| Priority date | — |
| Expiry date | Aug 14, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D1/2236
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) with a narrow bandwidth, and small phase noise which is particularly useful in a FM stereo decoder includes both analog and digital circuitry and has the advantages of both types of systems, performing better than standard PLL's without the need for any external components. An externally referenced digital voltage controlled oscillator, establishes the center frequency of the PLL while analog portions of the circuit permits accurate locking to the input signal and provides a high level of quietness of the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.