Pseudo line locked write clock for picture-in-picture video applications
US4970596A · kind A · utility
8Cited by
7References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 7, 1988 |
| Grant date | Nov 13, 1990 |
| Priority date | — |
| Expiry date | Sep 7, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/45
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The write clock controlling operation of the PIP circuitry (e.g. the analog digital converter in the PIP channel) utilizes a clock signal source having a substantially higher frequency (preferably six times) the desired write clock frequency. This clock signal is applied to a divide by six circuit which has a cycle reset controlled by the horizontal synchronization signal of the incoming PIP signal. The write clock signal furnished by this arrangement has the correct rate for sampling the incoming PIP video information and is pseudo line locked to the PIP horizontal synchronization signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.