Exception handling in a pipelined microprocessor
US4970641A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 1989 |
| Grant date | Nov 13, 1990 |
| Priority date | — |
| Expiry date | Apr 26, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for processing address translation exceptions occurring in a virtual memory system employing demand paging and having a plurality of registers and a real storage area, includes the steps of: (a) temporarily storing for each storage operation; (i) the effective storage address for the operation; (ii) exception control word information relative to the ones of the registers involved in the operation and the length and type of the operation; and (iii) any data to be stored during the operation; (b) retrieving the temporarily stored information to form an exception status block if an exception is generated indicating a failed operation; and (c) reinitiating the failed operation based on the information contained in the exception status block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.