Multiplier for binary numbers comprising a very high number of bits
US4970675A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 1989 |
| Grant date | Nov 13, 1990 |
| Priority date | — |
| Expiry date | Feb 15, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/723
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiplier for two binary values, X and Y, comprising a very high number (q) of bits, wherein memories storing the numbers X and Y and a result register MR are provided, X being expressed as the sequence of bits (x.sub.q-1 . . . x.sub.j . . . x.sub.0), uses the algorithm consisting in sequentially carrying out from j=q-1 to j=0 the additions 2R+x.sub.j Y and each time entering the result in the result memory (MR). In this multiplier the adders are grouped into n blocks of m bits (with n.times.m=q), m being chosen so that the carry transfer time into a block is lower than a clock period. Each block comprises a first and a second line of elementary adders forming the cells (C.sub.1 to C.sub.m+1) associated with each pair of bits to be added. This multiplier is more particularly adapted for carrying out the operations XYmodN and X.sup.S modN.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.