Circuit for controlling a flash EEPROM having three distinct modes of operation by allowing multiple functionality of a single pin
US4970692A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 1990 |
| Grant date | Nov 13, 1990 |
| Priority date | — |
| Expiry date | Feb 20, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An EEPROM receives a first address from a microprocessor. If the first address equals a first predetermined value, the EEPROM goes into a programming mode. If the first address equals a second predetermined value, the EEPROM goes into an erase mode. The EEPROM interprets a second address received from the microprocessor as indicating the location where data is to be stored in the EEPROM. The EEPROM generates an internal write pulse which remains active until the EEPROM receives a subsequent write instruction from the microprocessor. In this way, it is not necessary to generate a wait instruction to the microprocessor to halt the microprocessor while the EEPROM is storing data. Also, it is not necessary to provide additional circuitry to control whether the EEPROM goes into the erase or programming modes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.