Phase-lock loop circuit with improved output signal jitter performance
US4972160A · kind A · utility
16Cited by
6References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 7, 1989 |
| Grant date | Nov 20, 1990 |
| Priority date | — |
| Expiry date | Dec 7, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/085
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop has a phase detector which receives an input signal, a divided output signal from a VCO and a local clock signal, and produces a binary number representing the phase relationship between the input and divided signals. The binary number is applied to a microprocessor which compares it to a predetermined number n and controls the VCO through a D/A converter. To reduce output signal jitter, the microprocessor adjusts the VCO frequency so that the binary number alternates between n and n--1 or between n and n+1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.