Memory management for microprocessor system
US4972338A · kind A · utility
114Cited by
14References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1988 |
| Grant date | Nov 20, 1990 |
| Priority date | — |
| Expiry date | Apr 19, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Microprocessor architecture for an address translation unit which provides two levels of cache memory management is described. Segmentation registers and an associated segmentation table in main memory provide a first level of memory management which includes attribute bits used for protection, priority, etc. A second page cache memory and an associated page directory and page table in main memory provide a second level of management with independent protection on a page level. eyboard
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.