Apparatus for error detection and reporting on a synchronous bus
US4972345A · kind A · utility
10Cited by
0References
7Claims
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Assignee
Inventors
Key dates
| Filing date | Jan 9, 1989 |
| Grant date | Nov 20, 1990 |
| Priority date | — |
| Expiry date | Jan 9, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An error detection apparatus is implemented in a passive device inserted on a synchronous bus, linking two devices. The bus has data lines onto which data are transferred between the two devices under control of tag lines and clock signals which are companion of the transferred data. The apparatus allows errors to be detected, the failing device to be identified and the error signals to be reported in a psuedo-synchronous way on an error bus due to error detection and reporting logic circuits and a pseudo-synchronous timing circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.