Digital filter with integrated decimation
US4972357A · kind A · utility
12Cited by
2References
1Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 24, 1989 |
| Grant date | Nov 20, 1990 |
| Priority date | — |
| Expiry date | Feb 24, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0664
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital filter with integrated decimation shapes a sampled signal and reduces its sampling rate. The filter includes, in cascade, a prefilter (5), a decimator stage (8) and an equalizer (9). The prefilter is a simplified FIR filter in which only logical operations are performed; all multi-digit multiplications are performed only in the equalizer, at the reduced sampling rate. This results in a filter having increased throughput and/or occupying a reduced area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.