Semiconductor integrated circuit configured by using polycell technique
US4974049A · kind A · utility
8Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 7, 1988 |
| Grant date | Nov 27, 1990 |
| Priority date | — |
| Expiry date | Apr 7, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device configurated by using a polycell technique in which the wiring between the cell arrays is provided by two aluminum layers. The layers are insulated from each other by an insulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.